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 FDG8850NZ Dual N-Channel PowerTrench(R) MOSFET
April 2007
FDG8850NZ
Dual N-Channel PowerTrench(R) MOSFET
30V,0.75A,0.4
Features
Max rDS(on) = 0.4 at VGS = 4.5V, ID = 0.75A Max rDS(on) = 0.5 at VGS = 2.7V, ID = 0.67A Very low level gate drive requirements allowing operation in 3V circuits(VGS(th) <1.5V) Very small package outline SC70-6 RoHS Compliant
tm
General Description
This dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.
S2 G2 D1 D2 G1 S1 SC70-6 Pin 1 S1 G1 D2 Q2 Q1 D1 G2 S2
MOSFET Maximum Ratings TA = 25C unless otherwise noted
Symbol VDS VGS ID PD TJ, TSTG Parameter Drain to Source Voltage Gate to Source Voltage Drain Current -Continuous -Pulsed Power Dissipation for Single Operation Operating and Storage Junction Temperature Range (Note 1a) (Note 1b) Ratings 30 12 0.75 2.2 0.36 0.30 -55 to +150 Units V V A W C
Thermal Characteristics
RJA RJA Thermal Resistance, Junction to Ambient Single operation Thermal Resistance, Junction to Ambient Single operation (Note 1a) (Note 1b) 350 415 C/W
Package Marking and Ordering Information
Device Marking .50 Device FDG8850NZ Reel Size 7" Tape Width 8mm Quantity 3000 units
(c)2007 Fairchild Semiconductor Corporation FDG8850NZ Rev.B
1
www.fairchildsemi.com
FDG8850NZ Dual N-Channel PowerTrench(R) MOSFET
Electrical Characteristics TJ = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS BVDSS TJ IDSS IGSS Drain to Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V ID = 250A, referenced to 25C VDS = 24V, VGS = 0V VGS = 12V, VDS= 0V 30 25 1 10 V mV/C A A
On Characteristics
VGS(th) VGS(th) TJ rDS(on) gFS Gate to Source Threshold Voltage Gate to Source Threshold Voltage Temperature Coefficient Static Drain to Source On Resistance Forward Transconductance VGS = VDS, ID = 250A ID = 250A, referenced to 25C VGS = 4.5V, ID = 0.75A VGS = 2.7V, ID = 0.67A VGS = 4.5V, ID = 0.75A ,TJ = 125C VDS = 5V, ID = 0.75A 0.65 1.0 -3.0 0.25 0.29 0.36 3 0.4 0.5 0.6 1.5 V mV/C S
Dynamic Characteristics
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 10V, VGS = 0V, f= 1MHZ 90 20 15 120 30 25 pF pF pF
Switching Characteristics (note 2)
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain "Miller" Charge VGS =4.5V, VDD = 5V, ID = 0.75A VDD = 5V, ID = 0.5A, VGS = 4.5V,RGEN = 6 4 1 9 1 1.03 0.29 0.17 10 10 18 10 1.44 ns ns ns ns nC nC nC
Drain-Source Diode Characteristics and Maximum Ratings
IS VSD Maximum Continuous Drain-Source Diode Forward Current Source to Drain Diode Forward Voltage VGS = 0V, IS = 0.3A (Note 2) 0.76 0.3 1.2 A V
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RJA is determined by the user's board design.
a. 350C/W when mounted on a 1 in2 pad of 2 oz copper .
b. 415C/W when mounted on a minimum pad of 2 oz copper.
Scale 1:1 on letter size paper. 2. Pulse Test: Pulse Width < 300s, Duty cycle < 2.0%.
(c)2007 Fairchild Semiconductor Corporation FDG8850NZ Rev.B
2
www.fairchildsemi.com
FDG8850NZ Dual N-Channel PowerTrench(R) MOSFET
Typical Characteristics TJ = 25C unless otherwise noted
2.20
VGS = 2.7V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 4.5V
2.6
VGS = 2.0V VGS = 1.8V
1.76
ID, DRAIN CURRENT (A)
2.2 1.8 1.4 1.0 0.6 0.00
PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX
VGS = 2.0V
1.32 0.88 0.44 0.00 0.0
PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX
VGS =1.8V
VGS = 3.5V VGS = 2.7V
VGS = 1.5V
VGS = 4.5V
0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V)
2.0
0.44
0.88
1.32
1.76
2.20
ID, DRAIN CURRENT(A)
Figure 1. On-Region Characteristics
Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage
0.8
SOURCE ON-RESISTANCE ()
1.6
NORMALIZED DRAIN TO SOURCE ON-RESISTANCE
1.4 1.2 1.0 0.8 0.6 -50
ID = 0.75A VGS = 4.5V
ID =0.38A
PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX
rDS(on), DRAIN TO
0.6
TJ = 125oC
0.4
TJ = 25oC
-25
0
25
50
75
100
125
150
0.2
1
2
3
4
5
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On - Resistance vs Junction Temperature
2.20 1.76 1.32 0.88 0.44 0.00 0.0
TJ = 150oC TJ = 25oC TJ = -55oC
IS, REVERSE DRAIN CURRENT (A)
PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX VDD = 5V
Figure 4. On-Resistance vs Gate to Source Voltage
2
1
VGS = 0V
ID, DRAIN CURRENT (A)
0.1
TJ = 150oC TJ = 25oC
0.01
TJ = -55oC
0.5 1.0 1.5 2.0 VGS, GATE TO SOURCE VOLTAGE (V)
2.5
1E-3 0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward Voltage vs Source Current
(c)2007 Fairchild Semiconductor Corporation FDG8850NZ Rev.B
3
www.fairchildsemi.com
FDG8850NZ Dual N-Channel PowerTrench(R) MOSFET
Typical Characteristics TJ = 25C unless otherwise noted
VGS, GATE TO SOURCE VOLTAGE(V)
5
ID = 0.22A
200
100
CAPACITANCE (pF)
Ciss Coss
4 3 2 1 0 0.0
VDD = 10V VDD = 15V
VDD = 5V
10
Crss
f = 1MHz VGS = 0V
0.2
0.4 0.6 0.8 1.0 Qg, GATE CHARGE(nC)
1.2
1.4
1 0.1
1
10
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain to Source Voltage
50
4
ID, DRAIN CURRENT (A)
1
r DS
n) (o
T MI LI
100s 1ms
P(PK), PEAK TRANSIENT POWER (W)
ED
10
SINGLE PULSE RJA = 415OC/W TA = 25OC
0.1
SINGLE PULSE TJ = MAX RATED RJA = 415OC/W TA = 25OC
10ms
1
100ms 1s DC
0.01
0.005
0.1
1
10
100
0.1 0.0001 0.001
0.01
0.1
1
10
100
1000
Figure 9. Forward Bias Safe Operating Area
1
DUTY CYCLE-DESCENDING ORDER
VDS, DRAIN to SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
Figure 10. Single Pulse Maximum Power Dissipation
NORMALIZED THERMAL IMPEDANCE, ZJA
0.1
D = 0.5 0.2 0.1 0.05 0.02 0.01
PDM
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA o
0.01
SINGLE PULSE
RJA = 415 C/W
0.0001
0.001
0.01
0.1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (s)
Figure 11.
Transient Thermal Response Curve
(c)2007 Fairchild Semiconductor Corporation FDG8850NZ Rev.B
4
www.fairchildsemi.com
FDG8850NZ Dual N-Channel PowerTrench(R) MOSFET
tm
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx(R) Across the board. Around the worldTM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM E2CMOSTM EcoSPARK(R) EnSignaTM FACT Quiet SeriesTM FACT(R) FAST(R) FASTrTM FPSTM FRFET(R) GlobalOptoisolatorTM GTOTM HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM Motion-SPMTM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANAR(R) PACMANTM PDP-SPMTM POPTM Power220(R) Power247(R) PowerEdgeTM PowerSaverTM Power-SPMTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM The Power Franchise(R) TM
tm
TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM UHC(R) UniFETTM VCXTM WireTM
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
PRODUCT STATUS DEFINITIONS Definition of Terms
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Datasheet Identification Advance Information
Product Status Formative or In Design First Production
Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor.The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I26
(c)2007 Fairchild Semiconductor Corporation www.fairchildsemi.com


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